1. Field of the Invention
This invention relates to tape carriers for mounting and bonding a semiconductor chip on a substrate having interconnection circuitry, the tape carrier making electrical connections from the semiconductor chip having a pattern of electrodes formed on a main surface thereof to the circuitry formed on a substrate.
2. Description of the Related Art
Semiconductor chips, such as integrated circuit chips, have a plurality of projecting electrodes for making electrical connection to and from the chip. Such projecting electrodes or bumps are usually connected to a lead frame or a substrate having printed circuitry including interconnections by means of the wire bonding method. In recent years, however, wireless bonding methods are replacing the wire bonding method in certain areas of application. The tape automated bonding process utilizing tape carriers is one of the most promising and widely used among the wireless bonding methods.
FIG. 1 is a perspective view of an integrated circuit chip assembled on an electronic circuit board utilizing a conventional tape carrier, which is disclosed, for example, in Japanese Laid-Open patent applications 55-30859, 55-41775, 57-72360, 57-72361, and 58-1847451. The assemblage shown in FIG. 1 is as follows. An integrated circuit element or chip 1 having a plurality of projecting electrodes or bumps 1a, which are made, for example, of gold, and are formed on the upper surface thereof, is mounted on the electronic circuit substrate or board 2 on which an electrically conducting interconnection pattern 2a is formed. The bumps 1a are electrically connected to the terminal portions 2b of the conducting interconnection patterns 2a on the circuit board 2 through the finger-shaped leads 3b formed on the base film 3a, which together constitute the tape carrier 3. THe film 3a is made, for example, of a polyimide resin. The leads 3b are made of electrically conducting material such as copper foil and are carried on the film 3a. Inner lead portions 3c and outer lead portions 3d of the leads 3b extend horizontally from the square ring-shaped film 3a. The inner lead portions 3c are electrically connected to the bumps 1a and the outer lead portions 3d to the terminal portions 2b of the interconnection pattern 2a on the board 2. The circuit board 2 may be a printed circuit board or a liquid crystal display panel.
The assembling of the integrated circuits on circuit boards shown in FIG. 1 is effected as follows. The tape carrier utilized in the tape automated bonding process comprises an elongated tape-shaped film on which a sequence of lead patterns are formed. One pattern of the leads 3b of the sequence of such patterns is shown in FIG. 1. The tape-shaped film also has a sequence of patterns of apertures formed therein, each pattern of apertures forming a square ring-shaped film portion 3a carrying a set of leads 3b, as shown in FIG. 1. Thus, at the first stage of the assembly according to the tape automated bonding method, the inner lead portions 3c of the leads 3b, which are plated with tin, etc., are aligned on the bumps 1a on an integrated circuit chip 1, forwarding the elongated tape-shaped film. The inner lead portions 3c are then heated and pressed on the bumps 1a to form an alloy layer therebetween, so that the bumps 1a are bonded to the inner lead portions 3c of the leads 3b. As a result, the integrated circuit chip 1 is now carried by the tape-shaped film. Next, a square ring-shaped film and a pattern of leads are cut from the elongated tape-shaped film to obtain a set of leads 3b carried on the base film 3a as shown in FIG. 1. Further, the leads 3b are aligned on the corresponding terminal portions of the interconnection pattern 2a on the circuit board 2, and the outer lead portions 3d of the leads 3b are bonded thereto by means of soldering, etc.
The conventional assembling of the integrated circuit chips as described above has the following disadvantages. The leads 3b should be bonded to the bumps 1a at the inner lead portions 3c which are at the extreme end thereof. The leads 3b cannot be positioned and drawn over the upper main surface 1b of the integrated circuit chip 1. If portions of leads 3b are placed on the main upper surface 1b of the integrated circuit chip 1, on which circuit patterns, etc., are formed, an undesirable electrical contact may be formed between the leads 3b and the circuit patterns, etc., on the upper main surface 1b of the integrated circuit chip 1. Thus, the bumps 1a can only be electrically connected to the associated terminal portions of the interconnection pattern 2a of the board 2 which are situated in a close neighborhood of the bumps 1a to which they are connected.
The conventional assembling as described above has another disadvantage. Namely, if the input and output wirings to and from the integrated circuit chip which are coupled to the bumps 1a have a double layer structure, the interconnection patterns on 2a on the circuit board 2 should also have a double layer structure. It is, however, difficult to make the interconnection patterns double-layered when the electronic circuit board 2 is, for example, a liquid crystal display panel.
Thus, the conventional assembling of the integrated circuit chips as described above suffers grave limitations with regard to the possible electrical connections to and from the bumps thereof; the conventional method is not suited to a high-density assembling of the integrated circuit chips.